The present invention relates generally to semiconductors and more specifically the invention pertains to circuits for semiconductor dynamic random access memory (DRAM) cells which are an improvement over previously known two transistor cells by requiring fewer access lines and permitting more compact layout of the cells.
A dynamic memory is a type of semiconductor memory in which the presence or absence of an electrical capacitive charge represents the two states of a binary storage element. Field effect transistors are used as memory storage elements, where each bit is stored as a charge on a single transistor. This results in a high density storage with one transistor per bit. In such systems, the charge leaks and, therefore a typical dynamic memory must be refreshed by rewriting its entire contents.
The task of providing a dynamic semiconductor memory is alleviated, to some extent, by the systems disclosed in the following U.S. Patents, the disclosures of which are incorporated herein by reference:
U.S. Pat. No. 4,488,264 issued to Dshkhunian et al; PA1 U.S. Pat. No. 4,599,708 issued to Schuster; PA1 U.S. Pat. No. 4,771,323 issued to Sasaki; PA1 U.S. Pat. No. 4,926,378 issued to Uchida et al; PA1 U.S. Pat. No. 3,513,365 issued to Levi; and PA1 U.S. Pat. No. 3,634,825 issued to Levi.
Dshkunian et al disclose a transistor storage wherein the multidigit data buses are connected to write circuits and read amplifiers of a first readout direction and second readout direction. The write circuits are connected to the read bus and the read amplifiers are connected to the read bus.
Schuster discloses machine data storage with simultaneous write and read. A comparison identity is made of simultaneously timed write and read addresses. In response thereto, the normal read operation is inhibited while at the same time the write data signals are supplied as read data signals.
Sasaki discloses a semiconductor memory device wherein the potential to the word line is varied such that a first potential is applied for writing data, a second potential is applied for maintaining stored data, and a third potential is applied to read the stored data out.
Uchida et al disclose a bipolar static RAM having two wiring lines for each word line. A pair of layers form a pair of wiring lines corresponding together to a word line.
In view of the foregoing discussion, it is apparent that the development of dynamic random access memory elements represents an ongoing technological need. The present invention is intended to help satisfy that need.